/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#ifndef LNK_MPU_H
#define LNK_MPU_H
/********************************************* Define All Section Address Start *********************************************/
#define FLASH_BPT_START          (0x8000000)/* 4KB, Boot Package Table */
#define FLASH_BPT_END            (0x8000FFF)
#define FLASH_BL_START           (0x8001000)/*256KB, Bootloader */
#define FLASH_BL_END             (0x8040FFF)
#define FLASH_TEXT_START         (0x8041000)/* FLASHA_READONLY, 512KB, CR52+ Code */
#define FLASH_TEXT_END           (0x80C0FFF)
#define FLASH_CONST_START        (0x80C1000)/* 128KB, CR52+ Constant Data */
#define FLASH_CONST_END          (0x80E0FFF)
#define FLASH_DATA_INIT_START    (0x80E1000)/* 128KB, CR52+ Global Data Init */
#define FLASH_DATA_INIT_END      (0x8100FFF)
#define FLASH_FUNC_INIT_START    (0x8101000)/* 256KB, IRAM Func Inited */
#define FLASH_FUNC_INIT_END      (0x8140FFF)
/* no used by semidrive */
#define FLASH_LP_TEXT_START      (0x8141000)/* 128KB, LP Code */
#define FLASH_LP_TEXT_END        (0x8160FFF)
#define FLASH_LP_CONST_START     (0x8161000)/* 32KB, LP Constant Data */
#define FLASH_LP_CONST_END       (0x8168FFF)
#define FLASH_LP_DATA_START      (0x8169000)/* 16KB, LP Global Data Init */
#define FLASH_LP_DATA_END        (0x816CFFF)
#define FLASH_RESERVED2_START    (0x816D000)/* 16KB, Reserved2 */
#define FLASH_RESERVED2_END      (0x8170FFF)
#define FLASH_RESERVED3_START    (0x8171000)/* 6716KB, Reserved3 */
#define FLASH_RESERVED3_END      (0x87FFFFF)
#define FLASH_RESERVED_B_START   (0x8800000)/* 8192KB, Used for B bank */
#define FLASH_RESERVED_B_END     (0x8FFFFFF)
#define FLASH_DFLASH_START       (0x9000000)/* 512KB, Used for MRAM5 */
#define FLASH_DFLASH_END         (0x907FFFF)
#define FLASH_NORFLASH_START     (0x20000000)/* 64M, Used for Norflash */
#define FLASH_NORFLASH_END       (0x23FFFFFF)
#define CRAM_TEXT_START          (0x800000)/* 256KB, CRAM Fcuntion */
#define CRAM_TEXT_END            (0x83FFFF)
#define CRAM_XCP_START           (0x840000)/* 256KB, XCP Calibration Data */
#define CRAM_XCP_END             (0x87FFFF)
#define CRAM_RESERVED_START      (0x880000)/* 512KB, Reserved */
#define CRAM_RESERVED_END        (0x8FFFFF)
/* no used by semidrive end */
#define IRAM_BT_START            (0xA00000)/* 16KB, Reserved for Bootrom */
#define IRAM_BT_END              (0xA03FFF)
#define IRAM_FUNC_START          (0xA04000)/* 256KB, IRAM Function */
#define IRAM_FUNC_END            (0xA43FFF)
#define IRAM_NOCACHE_START       (0xA44000)/* 128KB, Non-Cacheable Data */
#define IRAM_NOCACHE_END         (0xA63FFF)
#define IRAM_DATA_START          (0xA64000)/* 128KB, Initialized Data */
#define IRAM_DATA_END            (0xA83FFF)
#define IRAM_BSS_START           (0xA84000)/* 496KB, Uninitialized Data */
#define IRAM_BSS_END             (0xAFFFFF)

#define IRAM_TEXT_START          (0xB00000)/* 256KB, IRAM Text */
#define IRAM_TEXT_END            (0xB7FFFF)
#define IRAM_CONST_START         (0xB80000)/* 128KB, Const Data */
#define IRAM_CONST_END           (0xB9FFFF)
#define IRAM_DATA_INIT_START     (0xBA0000)/* 128KB, Initialized Data Inited */
#define IRAM_DATA_INIT_END       (0xBBFFFF)
#define IRAM_FUNC_INIT_START     (0xBC0000)/* 256KB, IRAM Func Inited */
#define IRAM_FUNC_INIT_END       (0xBFFFFF)
#define IRAM_RESERVED_START      (0xC00000)/* 1M  IRAM3 reserved */
#define IRAM_RESERVED_END        (0xCFFFFF)
#define IRAM_LP_START            (0xF00000)/* 128K  IRAM_LP */
#define IRAM_LP_END              (0xF1FFFF)

#define CORE0TCMA_START          (0x11000000)/* 32KB, Core0 TCM A */
#define CORE0TCMA_END            (0x11007FFF)
#define CORE0TCMB_START          (0x11100000)/* 32KB, Core0 TCM B */
#define CORE0TCMB_END            (0x11107FFF)
#define CORE0TCMC_START          (0x11200000)/* 64KB, Core0 TCM C */
#define CORE0TCMC_END            (0x1120FFFF)
#define CORE1TCMA_START          (0x11400000)/* 32KB, Core1 TCM A */
#define CORE1TCMA_END            (0x11407FFF)
#define CORE1TCMB_START          (0x11500000)/* 32KB, Core1 TCM B */
#define CORE1TCMB_END            (0x11507FFF)
#define CORE1TCMC_START          (0x11600000)/* 64KB, Core1 TCM C */
#define CORE1TCMC_END            (0x1160FFFF)
#define CORE2TCMA_START          (0x11800000)/* 32KB, Core2 TCM A */
#define CORE2TCMA_END            (0x11807FFF)
#define CORE2TCMB_START          (0x11900000)/* 32KB, Core2 TCM B */
#define CORE2TCMB_END            (0x11907FFF)
#define CORE2TCMC_START          (0x11A00000)/* 64KB, Core2 TCM C */
#define CORE2TCMC_END            (0x11a0FFFF)
#define CORE3TCMA_START          (0x11C00000)/* 32KB, Core3 TCM A */
#define CORE3TCMA_END            (0x11c07FFF)
#define CORE3TCMB_START          (0x11D00000)/* 32KB, Core3 TCM B */
#define CORE3TCMB_END            (0x11D07FFF)
#define CORE3TCMC_START          (0x11E00000)/* 64KB, Core3 TCM C */
#define CORE3TCMC_END            (0x11E0FFFF)

#define MPU_M_TO_F_ADDR(addr)    ((addr)+0x7000000)
#define MPU_F_TO_M_ADDR(addr)    ((addr)-0x7000000)
#endif

